FIELD OF THE INVENTION
The present invention relates to planer field-effect transistors (FETs) formed n insulating or semi-insulating substrates, and more particularly to field-effect transistor structures which can suppress the influence as much as possible of charging and discharging due, to deep levels introduced into the substrate.
FETs using compound semiconductors such as GaAs and InP are usually fabricated on semi-insulating substrates. One of the reasons for this is that with these semiconductors it is difficult to obtain controlled low carrier concentration substrates due to impurity concentration or naturally occuring crystal defects, and the substrates become semi-insulating unless high concentration impurities are positively added. Another reason is that the semi-insulating substrate is convenient for high speed operation which is a feature of compound semiconductors because the electrostatic capacitance between it and transistors or interconnects is low. For the latter reason, semiconductor devices of silicon, which are required to preform high speed operation, are formed on insulating substrates such as those of SiO.sub.2 and sapphire.
The semi-insulating substrate is formed by introducing deep levels. With deep levels, charging and discharging are performed extremely slowly as compared to the transistor operation. With an element formed on silicon on insulator or semiconductor on insulator (hereinafter referred to as SOI), the same effects as above are obtained because interface levels are formed at the interface between the semiconductor and the insulator. This phenomenon poses no substantial problem so long as a single frequency is used. In the case of frequency mixers or in the case where a plurality of frequencies or wide-band signals involving such signals as pulse RF signals and digital signals are used, however, such problems as noise margin reduction and erroneous operation are posed by hysteresis of transistor characteristics. The phenomenon is usually observed as variations of the drain conductance G.sub.DS of transistor with frequency. In this specification, the phenomenon will be referred to as frequency dispersion of G.sub.DS or merely as frequency dispersion.
The occurrence of the frequency dispersion is attributable to the modulation of the FET current by the slow charging and discharging because of deep levels or interface levels because of the coupling of electric force lines due to the charge at the deep levels or the interface levels with FET channel charge. To solve this problem, it is conceivable to reduce the deep levels or interface levels such that the effects thereof can be ignored or to take the levels to a remote place where the effects can be ignored. In practice, however, a deep level called EL2 is always present in ordinary compound semiconductor substrates and, in SOI, it is difficult to completely eliminate the interface levels even by using thermal oxide films. In order to take the levels to a place remote from the transistor channel, it is necessary to form a high purity, thick epitaxial growth film. However, it is difficult to form a high purity thick layer even by using such epitaxial growth processes as MBE. Therefore, the above method is practically almost infeasible.
Accordingly, it has been proposed to cut electric force lines from the deep levels or interface levels by providing a conductive layer between the channel and the deep levels or interface levels and producing a constant potential on the conductive layer. It is necessary, however, to hold such a shield layer at a constant potential. In other words, shield layer potential variations will constitute variations of transistor current, and thus it is not possible to achieve the intended suppression of the frequency dispersion. It is conceivable to hold the shield layer at a constant potential by making a direct electrical contact to it. The formation of the contact to the shield layer, however, is accompanied by such problems as complication of the fabrication process and chip area increase. Accordingly, a process for an easier method of fixing the shield layer potential is needed.